Technical Field
The present disclosure relates to resistive memories, and more generally memories in which each memory cell comprises a selection gate and a variable-impedance element able to exhibit a number of different states detectable by an impedance measurement. Depending on whether the element preserves its state when its supply of electric power is turned off, the memory is either volatile or nonvolatile.
Description of the Related Art
Thus, a number of types of resistive memories are being developed. In CBRAMs (conductive-bridging random access memories), the variable-impedance element comprises two electrodes and a thin layer of solid electrolyte placed between the electrodes. Under the effect of biasing of the element, metal ions migrate from one of the two electrodes and from the electrolyte towards the other electrode, and form one or more filaments that decrease the electrical resistance of the element.
RRAM or ReRAM (resistive RAM) memories comprise a dielectric element that may be made to conduct reversibly by forming conductive filaments obtained by applying a sufficiently high voltage. In particular, OxRAM memories use metal oxides (Ox) as the material of the resistance which may be controlled reversibly.
In FeRAM or FRAM (ferroelectric RAM) memories, the variable-resistance element comprises a capacitor the dielectric of which is a ferroelectric material in which magnetic dipoles may be oriented along field lines of an electric field formed between the electrodes when the capacitor is charged. When the capacitor discharges, the dipoles preserve their orientation.
The variable-resistance element of magnetoresistive RAM (MRAM) memories comprises two plates made of ferromagnetic material able to produce an electric field, separated by a dielectric film. One of the plates is a permanent magnet, whereas the other plate generates a magnetic field that may be modified by an electric current. The state of the memory cell is read via a resistance measurement.
FIGS. 1A and 1B schematically show in cross section a semiconductor substrate SUB on which has been formed a memory cell MC comprising a variable-resistance element VZ. FIG. 1A is a longitudinal view in cross section along the plane AA′ indicated in FIG. 1B, and FIG. 1B is a transverse view in cross section along the plane BB′ indicated in FIG. 1A. The memory cell MC comprises a selection transistor comprising a gate GT, drain DDP and source SDP regions on either side of the gate GT, and a channel region under the gate GT between the drain DDP and source SDP regions. The gate GT is produced in a layer made of polysilicon formed on an insulating layer GO deposited on the substrate SUB. The regions DDP, SDP are formed by implanting dopants into the substrate SUB on each side of the gate GT. The memory cell MC is covered with a dielectric insulator D1. The source region SDP is connected to a source line SL by way of a via passing through the insulating layer D1. The gate GT forms a word line WL lying parallel to the source line SL. The variable-resistance element VZ is formed in the insulating layer D1 and is connected to the drain region DDP by way of a via formed in the insulating layer D1. The variable-resistance element VZ is connected to a bit line BL formed on the surface of the insulating layer D1, by way of a via BC formed in the insulating layer D1. The bit line BL runs perpendicular to the word line WL and source line SL. The memory cell is isolated from adjacent memory cells (or other circuit elements formed on the substrate SUB) by shallow trench isolations STI1 parallel to the gate GT, and shallow trench isolations STE perpendicular to the gate GT. The trench isolations STI1 may be replaced by transistor gates (such as the gate GT) biased so as to maintain the associated transistor in the off state.
FIG. 2 shows the electric circuit of one portion of a memory plane comprising memory cells such as the memory cell MC shown in FIGS. 1A and 1B. The memory plane comprises word lines WL, source lines SL parallel to the word lines WL and bit lines perpendicular to the word lines WL and to the source lines SL. Each memory cell MC comprises a selection transistor ST comprising a (source or drain) conduction terminal connected to one terminal of a variable-resistance element VZ, the other terminal of which is connected to one of the bit lines BL. The other conduction terminal of the selection transistor ST is connected to one of the source lines SL, and the gate terminal of the transistor ST is connected to one of the word lines WL.
To decrease the area occupied by each memory cell, it has been proposed to produce the memory cells in pairs sharing a single conduction region connected to one source lines, as in FIG. 2. In this embodiment, the trench isolation STI1 to the left in FIG. 1A is replaced by a gate, such as the gate GT, forming the gate of the selection transistor of the other memory cell of the pair of memory cells.
It would be desirable to further decrease the substrate area occupied by a memory cell comprising a variable-resistance element.